1. Technical Field
The present disclosure relates to an edge termination structure for a power integrated device, for example a power MOS transistor or a power diode, in particular made, at least in part, in a substrate including silicon carbide. The present disclosure further regards a corresponding manufacturing process.
2. Description of the Related Art
In a known way, silicon carbide (SiC) has advantageous electrical properties, such as a wide bandgap, a high critical electrical field and a high thermal conductivity, which render its use particularly promising for high-power, high-voltage, fast-switching and high-operating-temperature applications.
It is further known that the breakdown voltage of power integrated devices suffers, in the edge termination region, from the so-called effect of thickening of the electric-field lines, which tends to limit the maximum theoretical value of the breakdown voltage. This evidently occurs both in the case of devices made in a silicon substrate and in devices made in a silicon-carbide substrate.
The development of an effective edge termination structure, that allows reaching a breakdown voltage close to the theoretical values, is an important consideration in the design of power integrated devices.
In the past, a wide range of solutions of termination structures has been proposed, with the purpose of mitigating the edge effects.
In general, the techniques proposed envisage suitable modification of the distribution of the electric field at the boundary of the main junction of the power integrated device, for exploiting at best the edge region, reducing the peak value of the surface electric field to a minimum.
For instance, as shown in FIG. 1, a known edge termination solution envisages providing, in a substrate (or structural layer) 1 a power integrated device (for example, including silicon carbide) and a ring region 2, which is connected, joined, to a main junction region 3 of the power integrated device, at the edge region.
It should be noted that by the expression “main junction region” is meant a doped region of the device, provided in the active area and bordering on the edge region, which forms with the substrate 1 a semiconductor junction, functional to the operations performed by the power integrated device; further, by “ring region” is meant a doped edge termination region, generally but not necessarily having an overall ring shape (with circular, square, rectangular, or in general polygonal cross-section) that surrounds the main junction region, or in general an active area of the power integrated device.
A metal region 4, referred to as “field-plate region” is present on the substrate 1, and is arranged directly in contact with the main junction region 3 and is separated from the ring region 2 by a field-oxide region 5.
The depth in the substrate 1 of the ring region 2 may be lower (as shown in FIG. 1), or alternatively higher (in a way not illustrated herein), than the depth of the main junction region 3.
This solution has the advantage of being simple to manufacture, given the use of just one mask and just one dopant implantation to obtain and dope the ring region 2. However, this solution does not afford an optimal control of the distribution of the electric field (generally, peaks of electric field may be found in the proximity of the end of the metal region 4 and of the ring region 2).
A further solution that has been proposed envisages, as shown in FIG. 2, providing in the substrate 1 a plurality of ring regions, designated by 2a, 2b, 2c and 2d in the example.
One of the ring regions, in the example the ring region 2a, is arranged in contact with the main junction region 3 and once again may have depth higher (as shown in FIG. 2), or alternatively lower (in a way not illustrated herein), than the depth of the main junction region 3.
Ring regions 2a-2d have a variable width W, as likewise variable is the distance of separation S between the same ring regions 2a-2d; in the design stage, one or both of the characteristics of width W and distance of separation S may be appropriately sized to obtain a desired profile of the electric field at the edge termination region.
This solution has the advantage of enabling in this way a better control of the electric field, albeit maintaining a good degree of manufacturing simplicity, envisaging once again use of just one mask and just one dopant implantation.
However, peaks of electric field are present in the areas of transition between the ring regions 2a-2d, the presence of which jeopardizes performance.
More complex edge termination structures have further been proposed, which envisage, for example, providing so-called floating guard rings, VLD (variation in lateral doping) rings, variable-transparency rings, mesa-etching structures, structures with lateral junction extension (JTE).
Some of these solutions have been implemented also in the field of power integrated devices made in silicon-carbide substrates, appropriately adapted to take into account the peculiar electrical characteristics of the silicon carbide itself. In general, however, direct transfer of the edge termination techniques from silicon to silicon carbide is somewhat problematical, on account of the different properties of the two materials and of the consequent different manufacturing techniques and of the different electrical behavior.
Among these properties, for example, the lower diffusiveness of the dopants within silicon carbide as compared to silicon is known.
In general, none of the edge termination structures of a known type is thus optimized for use in power integrated devices made in silicon-carbide substrates.